Testable Design of BiCMOS Circuits for Stuck-Open Fault Detection Using Single Patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (+OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skewddelays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the twopattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.